1. Field of the Invention
The present invention relates to a semiconductor structure for the protection of integrated circuits from ESD pulses.
2. Description of the Related Art
If electrically charged subjects or persons are brought into contact with an input or output of an integrated circuit, a discharge can take place, where a current exceeding the standard measure flows through to the integrated circuit and a high voltage drops across the same. This can possibly lead to the destruction of the integrated circuit.
For the protection of integrated circuits from these electrical discharges, so called ESD pulses (ESD=electrostatic discharge) the inputs and outputs of the integrated circuits are provided with protective structures, which are to guarantee a safe drain of the discharge currents.
Therefore, in some applications, a pnp bipolar transistor is used as a protective structure, where the base is not connected, i.e., the base “floats”. If an ESD pulse reaches such a pnp bipolar transistor, the same breaks down. Thereby, however a low voltage is to drop across the broken-down pnp bipolar transistor, since the integrated circuit to be protected is connected in parallel and thus experiences the same voltage. A voltage drop, which is too high, could lead to breakdowns of the integrated circuit.
Therefrom, the requirement results that the resistance of the pnp bipolar transistor is to be as low as possible so that only a low voltage drops across the same.
The resistance could be lowered by increasing the base doping.
On the other hand, the base doping of the pnp bipolar transistor should not be too high, since, during standard operation, the transistor may only break above its operating voltage. Thus, a certain maximum doping of the base cannot be exceeded. Therefrom, a minimum resistance results and thus a minimum voltage drop across the pnp bipolar transistor in the ESD case.